Thermal warp compensation ic package

ABSTRACT

An apparatus and method for temperature induced warpage compensation in an integrated circuit package is disclosed. The apparatus consists of bonded layers of material having different thermal coefficients of expansion. The bonded layers are bonded to the top of the integrated circuit package. By appropriate choice of temperature coefficients the layers of material can compensate for either convex or concave warpage. In some embodiments the layers of material have apertures therein allowing compensation for more complex warpages. As well, in some embodiments the top layer of material does not have a planar cross-section. A method is also disclosed for manufacturing an integrated circuit package assembly. The apparatus and method provide an alternative to methods of dealing with IC package warpage known in the art.

FIELD OF THE INVENTION

The invention relates to warping of integrated circuit (IC) packagesduring manufacturing processing and is particularly concerned withproviding a means for generally neutralizing the warpage by use of acounter-warping element.

BACKGROUND OF THE INVENTION

A wide variety of semiconductor packages having integrated circuits (IC)are used in industry. In general, ICs and their packages have beenbecoming more complex over time, with the result that their power, speedand their size has been increasing. With increased size and complexityalso arise an increased number of connections from the integratedcircuit to the larger electronics assembly of which it is a part.Historically, pin counts of Very Large Scale Integrated (VLSI) circuitsexceeded the limits for dual in-line packaging (DIPs), leading todevelopment of the Pin Grid Array (PGA). In the PGA the inputs andoutputs of the integrated circuit are connected to an integrated circuitpackage in which pins are arranged in a square array that may cover upto the entire bottom of the package. The pins conduct electrical signalsfrom the integrated circuit to the printed circuit board (PCB) in whichor on which the IC package is mounted. A subsequent development to thePGA is that of the Ball Grid Array, or BGA, in with the pins arereplaced by balls of solder affixed to the bottom of the integratedcircuit package. During assembly to the printed circuit board, the BGAand printed circuit board are heated, causing the solder balls to meltand solder the integrated circuit package to the printed circuit board.

As the BGA packaging offers additional advantages, such as improved heatconduction due to the lower thermal resistance between the package andPCB, a lower inductance connection than pins, and reduced solderconnection bridging; it has become a preferred packaging type.

One disadvantage of BGAs however, is the requirement for flatness duringprocessing. In general, the solder connections require a tightmechanical tolerancing during processing in order to preclude mechanicalstresses which would promote solder joint failure.

Working against this requirement, however, is the difference in thermalcoefficient of expansion which exists between the substrate upon whichthe solder balls are mounted, and the silicon integrated circuit mountedupon the substrate. The differences in the thermal coefficient ofexpansion lead to warpage of the BGA package as a whole. This warpage,which for the purposes of this specification refers to a bending ortwist or general lack of flatness in the overall integrated circuitpackage, including in particular the plane formed by the solder jointlocations, can cause a variety of problems. A non-exhaustive list by wayof example includes problems such as fractured solder joints, opencontact solder joints, pillowed joints, or intermittent contact solderjoints.

The problem of warpage is exacerbated by larger package sizes, and byelevated processing temperatures. As trends in integrated circuitcomplexity are consistently in the direction of larger package sizes,and as production changes in the direction of lead free solders yieldhigher processing temperatures, the problem of integrated circuitwarpage is a pressing one. It is important to note that the desiredtolerance for flatness at and across the processing temperature rangecan be very high. For example, for BGA packages having a size of greaterthan 1″ across, there may be a maximum warpage tolerance of on the orderof 0.008″ allowed.

One prior solution to the problem of IC package warping has been theincorporation on top of the IC of a flat stiffener plate. The stiffenerplate takes the form essentially of a completely flat entirely planaritem having a constant thickness, and is a simple quadrilateral havingapproximately its perimeter as the size of the IC package perimeter whenviewed from the top. A central region of the flat stiffener plate may becut out in certain applications, for example to allow access of athermally conductive element.

However, these stiffener flat plates suffer from the disadvantage thatthey themselves are entirely flat, and thus, have a somewhat limitedresistance to warping due to temperature change or torsion or bendingforces. In order to make a flat plate strong enough to provide desirableresistance to warping in the overall IC package, it can be necessary tomake the stiffening plate undesirably thick. It is undesirable for thestiffening plate, which rests on top of the IC, to be too thick becausethe thick stiffening plate, on top of and added to the IC thickness,causes the entire assembled IC package to be thick, thus potentiallylimiting IC packaging placement options and/or increasing printedcircuit card to printed circuit card separation in the final systemassembly.

Further, the added stiffener thickness increases the IC die-to-lidspacing, thereby creating a larger separation that needs to be filledwith thermal interface material, the longer thermal path ultimatelyimpeding thermal dissipation from the IC. Moreover, because of thestiffener's entirely flat cross-sectional profile, increased stiffnessis achieved inefficiently though the increase of the overall volume ofmaterial, thus adding additional cost and weight to the final ICpackage.

In view of the foregoing, it would be desirable to provide a means ofdecreasing warpage of IC packages. In particular, it would be desirableto provide a means that can provide improved performance and/or mountingreliability while providing a desirable low degree of thickness and/or adesirable low amount of material.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a temperature responsivewarpage counteracting integrated circuit assembly.

According to an aspect of the invention there is provided a temperatureresponsive warpage counteracting integrated circuit assembly for usewith an integrated circuit package having a connection grid side and atop side. The integrated circuit assembly has a first layer of a firstmaterial having a first coefficient of temperature expansion and a firstand second surface; a second layer of a second material having a secondcoefficient of temperature expansion different from the firstcoefficient of temperature expansion and a first and second surface; thefirst surface of the second layer is bonded to the second surface of thefirst layer; and the second surface of the second layer is bonded to thetop side of the integrated circuit package.

In some versions of this embodiment the first coefficient of temperatureexpansion is greater than the second coefficient of temperatureexpansion, while in other embodiments the second coefficient oftemperature expansion is greater than the first coefficient oftemperature expansion.

Advantageously, in some versions of this embodiment there may beapertures in the first and second layers, and in some versions theseapertures are of a similar size and aligned.

Advantageously, in some versions the first layer may have aplanar-convex cross-section with the planar portion at the secondsurface. In other versions of this embodiment the first layer may have aplanar-concave cross-section with the planar portion at the secondsurface.

In another embodiment of the invention there is provided a temperatureresponsive warpage counteracting integrated circuit assembly for usewith an integrated circuit package having a connection grid side and atop side. The integrated circuit assembly has a layer of a materialhaving a coefficient of temperature expansion that varies from a firstvalue at a first surface to a second value at a second surface; and thesecond surface of the layer of material is bonded to the top side of theintegrated circuit package. In some versions of this embodiment thefirst value is larger than the second value, while in other versions thesecond value is larger than the first value.

Advantageously, in some versions of this embodiment the layer has anaperture therein. Also advantageously, in some versions of thisembodiment the layer has a planar-convex or planar-concave cross-sectionwith the planar portion being at the surface bonded to the integratedcircuit package.

In another embodiment of the invention there is provided a method ofmanufacture of a temperature responsive warpage counteracting integratedcircuit assembly for use with an integrated circuit package having aconnection grid side and a top side. The method has the steps ofproviding a first layer of a first material having a first coefficientof temperature expansion and a first and second surface; providing asecond layer of a second material having a second coefficient oftemperature expansion different from the first coefficient oftemperature expansion and a first and second surface; bonding the firstsurface of the second layer to the second surface of the first layer;and bonding the second surface of second layer to the top side of theintegrated circuit package.

In some versions of this embodiment, there is the step of providing thatthe first coefficient of temperature expansion is greater than thesecond coefficient of temperature expansion. In other versions of thisembodiment there is the step of providing that the second coefficient oftemperature expansion is greater than said the coefficient oftemperature expansion.

Advantageously, in some versions of this embodiment there are theadditional steps of providing a first aperture in the first layer; andproviding a second aperture in the second layer, wherein the secondaperture is of generally the same size as the first aperture, andaligned with the first aperture.

In yet another embodiment of the invention there is provided a method ofmanufacture of a temperature responsive warpage counteracting integratedcircuit assembly for use with an integrated circuit package having aconnection grid side and a top side, the method having the steps ofproviding a layer of a material having a coefficient of temperatureexpansion that varies from a first value at a first surface to a secondvalue at a second surface; and bonding the second surface of the layerof material to the top side of the integrated circuit package. In someversions of this embodiment there is the step of providing that thefirst value is greater than the second value. In other versions of thisembodiment there is the step of providing that the second value isgreater than the first value.

Advantageously, in some versions of this embodiment there is theadditional step of providing an aperture in the layer of material.

Note: in the following the description and drawings that follow merelyillustrate the principles of the invention. It will thus be appreciatedthat those skilled in the art will be able to devise variousarrangements that, although not explicitly described or shown herein,embody the principles of the invention and are included within itsspirit and scope. Furthermore, all examples recited herein areprincipally intended expressly to be only for pedagogical purposes toaid the reader in understanding the principles of the invention and theconcepts contributed by the inventors to furthering the art, and are tobe construed as being without limitation to such specifically recitedexamples and conditions. Moreover, all statements herein recitingprinciples, aspects, and embodiments of the invention, as well asspecific examples thereof, are intended to encompass equivalentsthereof.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be further understood from the followingdetailed description of embodiments of the invention, with reference tothe drawings in which:

FIG. 1 a illustrates a cross-sectional drawing of an integrated circuitpackage which in accordance with the prior art;

FIG. 1 b illustrates a cross-sectional drawing of the integrated circuitpackage of FIG. 1 a which is showing a concave warpage due to elevatedtemperature;

FIG. 1 c illustrates an exploded cross-sectional drawing of anintegrated circuit package and a warpage compensation element inaccordance with an embodiment of the present invention;

FIG. 1 d illustrates a cross-sectional drawing of the integrated circuitpackage and the warpage compensation element of FIG. 1 c bonded togetherin accordance with an embodiment of the present invention;

FIG. 2 a illustrates another cross-sectional drawing of an integratedcircuit package in accordance with the prior art;

FIG. 2 b illustrates a cross-sectional drawing of the integrated circuitpackage of FIG. 2 a which is showing a convex warpage due to elevatedtemperature;

FIG. 2 c illustrates an exploded cross-sectional drawing of anintegrated circuit package and a warpage compensation element inaccordance with another embodiment of the present invention;

FIG. 2 d illustrates a cross-sectional drawing of the integrated circuitpackage and warpage compensation element of FIG. 2 c bonded together inaccordance with an embodiment of the present invention;

FIG. 3 a illustrates an isometric drawing of an integrated circuitpackage in accordance with the prior art; and

FIG. 3 b illustrates an isometric drawing of the integrated circuitpackage of FIG. 3 a with a warpage compensation element bonded theretowhere the warpage compensation element has an aperture.

In the following figures, like features bear similar reference labels.

DETAILED DESCRIPTION

Referring now to the drawings, in which like numerals refer to likecomponents or steps, there are disclosed broad aspects of variousexemplary embodiments.

Many embodiments relate to a warpage reducing element that can beattached to an integrated circuit (IC) package. As used throughout thisdocument, the terms IC (integrated circuit) and IC packaging are usedinterchangeably to make reference to the overall component assembly,which is also commonly referred to as the IC package. Examples of ICpackages include for example TSOPS, QFPs, SOIC, BGA, CCGA, etc. It isnoted that for packages containing above approximately 400 connections,IC packaging almost exclusively take on the form of Area Array stylepackaging, which itself can include various subtypes, such as forexample Column Grid Arrays (CCGA), Pin Grid Arrays (PGA), and Ball GridArrays (BGA). The stiffener solutions that are described herein areapplicable to such Area Array devices, including for example BGAs. Theterm IC assembly is used herein to refer to an IC or IC package that hasa warpage reducing element incorporated therein or mounted thereto.

When referring herein to a plane, the reference includes the concept ofa flat plate, which actually has a top and bottom flat surface and somethickness, with the top and bottom flat surfaces technically lying alongparallel planes. Planar herein includes the concept of a plate beingplanar although it has such a thickness. Additionally, when referringherein to a planar-convex cross-section, the reference includes theconcept of a plate having a flat bottom and a convex top surface.Likewise, when referring herein to a planar-concave cross-section, thereference includes the concept of a plate having a flat bottom and aconcave top surface.

Referring to FIG. 1 a there may be seen an integrated circuit 12 with aplurality of solder bumps 14. The solder bumps are for makingconnections to pads at a mounting location, for example on a printedcircuit board.

Referring to FIG. 1 b there may be seen the integrated circuit 12 withan exaggerated depiction of the warpage effect of a high temperature.Such a high temperature may occur during processing, for example whenthe integrated circuit is being mounted on a printed circuit board. Inthe case of processing with lead free solders, this high temperature maybe on the order of 260° C. In this case the resulting warpage is concavein nature. The warpage generally results from a mismatch between thethermal coefficient of expansion of the silicon integrated circuit dieand the thermal coefficient of expansion of the IC carrier to which thesilicon die is affixed.

Referring to FIG. 1 c there may be seen an integrated circuit 22. Alsodepicted is an assembly of materials having a first layer 26 and asecond layer 28. Layers 26 and 28 are bonded together over theircojoined surfaces. In FIG. 1 c, first layer 26 has a thermal coefficientof expansion which is larger than the thermal coefficient of expansionof second layer 28. Due to the differences in their respective thermalcoefficient of expansion, a positive change in temperature will resultin a greater degree of expansion of layer 26 than of cojoined layer 28.The net result of this greater degree of expansion, coupled with thecojoining of the layers is to induce a warpage in the combined layerswhich is opposite in nature to the warpage of the integrated circuit 12in FIG. 1 b.

Referring to FIG. 1 d there may be seen the resulting temperatureresponsive warpage counteracting integrated circuit assembly whereinlayer 28 is bonded to the surface of integrated circuit 22. This bondingmay be effected by appropriate adhesives.

Alternatively, according to another embodiment of the invention, layer28 may be built up via plating the surface of integrated circuit 22, andlayer 26 established by plating the surface of layer 28.

Alternatively, according to yet another embodiment of the invention,layer 28 may be built up via plating the surface of integrated circuit22, and layer 26 bonded to the surface of layer 28 by an appropriateadhesive.

Referring now to FIG. 2 a there may be seen an integrated circuit 212with a plurality of solder bumps 214. As previously described, thesolder bumps are for making connections to pads at a mounting location,for example on a printed circuit board.

Referring to FIG. 2 b there may be seen the integrated circuit 212 withan exaggerated depiction of the warpage effect of a high temperature. Inthis case the resulting warpage is convex in nature. This warpagegenerally results where the mismatch between the thermal coefficient ofexpansion of the silicon integrated circuit die and the thermalcoefficient of expansion of the IC carrier to which the silicon die isaffixed is opposite in nature to the situation depicted in FIG. 1 b.

Referring to FIG. 2 c there may be seen an integrated circuit 222. Alsodepicted is an assembly of materials having a first layer 228 and asecond layer 226. Layers 228 and 226 are bonded together over theircojoined surfaces. In FIG. 2 c, first layer 228 has a thermalcoefficient of expansion which is smaller than the thermal coefficientof expansion of second layer 226. Due to the differences in theirrespective thermal coefficient of expansion, a positive change intemperature will result in a greater degree of expansion of layer 226than of cojoined layer 228. The net result of this greater degree ofexpansion, coupled with the cojoining of the layers is to induce awarpage in the combined layers which is opposite in nature to thewarpage of the integrated circuit 212 in FIG. 2 b.

Referring to FIG. 2 d there may be seen the resulting temperatureresponsive warpage counteracting integrated circuit assembly whereinlayer 226 is bonded to the surface of integrated circuit 222. Thisbonding may be effected by appropriate adhesives.

Alternatively, according to another embodiment of the invention, layer226 may be built up via plating the surface of integrated circuit 222,and layer 228 established by plating the surface of layer 226.

Alternatively, according to yet another embodiment of the invention,layer 226 may be built up via plating the surface of integrated circuit222, and layer 228 bonded to the surface of layer 226 by an appropriateadhesive.

Referring now to FIG. 3 a there may be seen an isometric depiction ofintegrated circuit 312. As previously described, the solder bumpsvisible on the lower surface of integrated circuit 312 are for makingconnections to pads at a mounting location.

Referring now to FIG. 3 a there may be seen an isometric depiction ofintegrated circuit 312. As previously described, the solder bumpsvisible on the lower surface of integrated circuit 312 are for makingconnections to pads at a mounting location.

Referring now to FIG. 3 d, there may be seen an isometric depiction ofthe resulting temperature responsive warpage counteracting integratedcircuit assembly wherein a first layer 326 is bonded to the surface ofintegrated circuit 322, and a second layer 328 is bonded to first layer326. In this embodiment, an aperture 330 has been provided which piercesboth first layer 326 and second layer 328. This aperture 326 willrelieve the bending forces provided by the mismatched thermalcoefficients of expansion of first layer 326 and second layer 328. Sucha relief may be useful in situation wherein there is little warpage inthe vicinity of the silicon die, and thus warpage counteractingcompensation is unnecessary. Such apertures may also be useful inembodiments wherein more complex warpages than simple convex or simpleconcave warpages exist. As the counteracting forces tend to zero forcein the vicinity of the aperture, warpage compensation can be tailoredmore precisely to the needs of a particular integrated circuit package.

According to yet another embodiment of the invention, the topmost layer,for example layer 26 in FIG. 1 d, or layer 228 in FIG. 2 d, is not ofuniform thickness. In this embodiment, a cross-section of the topmostlayer is in the form of a planar-convex section, or a planar-concavesection. The planar portion of the section is on the face cojoined withthe lower layer. By varying the thickness of the topmost layer,additional degrees of expansion over specific regions of the integratedcircuit package may be established. This embodiment thus offers afurther provision for fine tuning the warpage counteraction forcesaccording to the needs of the specific integrated circuit package.

The choice of materials for the layers is ultimately dictated by factorsincluding considerations of cost, availability, and compatibility withmanufacturing processes. Possible material choices include pairings suchas copper/steel, and aluminum/copper. Other materials which may be ofinterest include stainless steel because of its low reactivity andInvar™ because of its low coefficient of thermal expansion. In terms ofthickness, material layers having an overall thickness in the range of0.5 mm to 1.5 mm are suitable, however it is contemplated that greaterand lesser thicknesses could be of use in particular circumstances.

By way of example, one prototype warpage counteracting element modeledwas formed of a first layer of steel having a thickness of 1.2 mm, and asecond layer of copper having a thickness of 0.1 mm. The overallthickness was the sum of these layers yielding a 1.3 mm thick element.This element, sized to that of an IC package, produced a curvature of0.0107″ (0.27 mm) over a 200° C. temperature shift, which isrepresentative of both the order of magnitude of package curvatureswhich need to be counteracted, and of the temperature delta between roomtemperature ambient and solder reflow processing temperatures.

According to yet another embodiment of the invention, a single layer ofmaterial is provided for bonding to the surface of the integratedcircuit package. This single layer of material is formulated so that thethermal coefficient of expansion of the layer of material varies from afirst value at one surface, to a second value at the other surface. Suchvariation may be induced by, for example, loading a material matrix withvarying densities of filler. The net effect of the variation in thermalcoefficient of expansion across the depth of the material results inbending forces similar to that of the two layer embodiment. The use ofsuch a formulated material may be applicable to situations where asuitable combination of paired coefficients of thermal expansion cannotbe found.

In summary, an apparatus has been disclosed which provides a means tocounteract the warpage of integrated circuit packages at elevatedtemperatures. In some embodiments the apparatus consists of a cojoinedpair of layers of material having mismatched coefficients of thermalexpansion, where the layers are bonded to the surface of the integratedcircuit package. In some embodiments the topmost layer is non-planar. Inother embodiments, at least one aperture is let into the two layers. Inone disclosed embodiment, a formulated material having a thermalcoefficient of expansion which varies from one surface to the othersurface is used in place of the two layers.

It is to be understood that various changes in the details, materials,and arrangements of the parts which have been described and illustratedin order to explain the nature of this invention may be made by thoseskilled in the art without departing from the scope of the invention asexpressed in the following claims.

It should also be understood that the steps of the exemplary methods setforth herein are not necessarily required to be performed in the orderdescribed, and the order of the steps of such methods should beunderstood to be merely exemplary. Likewise, additional steps may beincluded in such methods, and certain steps may be omitted or combined,in methods consistent with various embodiments of the present invention.

Although the elements in the following method claims, if any, arerecited in a particular sequence with corresponding labeling, unless theclaim recitations otherwise imply a particular sequence for implementingsome or all of those elements, those elements are not necessarilyintended to be limited to being implemented in that particular sequence.

Reference herein to “one embodiment” or “an embodiment” means that aparticular feature, structure, or characteristic described in connectionwith the embodiment can be included in at least one embodiment of theinvention. The appearances of the phrase “in one embodiment” in variousplaces in the specification are not necessarily all referring to thesame embodiment, nor are separate or alternative embodiments necessarilymutually exclusive of other embodiments. The same applies to the term“implementation.” Numerous modifications, variations and adaptations maybe made to the embodiment of the invention described above withoutdeparting from the scope of the invention, which is defined in theclaims.

1. A temperature responsive warpage counteracting integrated circuitassembly for use with an integrated circuit package having a connectiongrid side and a top side, said integrated circuit assembly comprising: afirst layer of a first material having a first coefficient oftemperature expansion and a first and second surface; a second layer ofa second material having a second coefficient of temperature expansiondifferent from said first coefficient of temperature expansion and afirst and second surface; said first surface of said second layer bondedto the second surface of said first layer; and said second surface ofsecond layer bonded to the top side of said integrated circuit package.2. A temperature responsive warpage counteracting integrated circuitassembly as claimed in claim 1 wherein said first coefficient oftemperature expansion is greater than said second coefficient oftemperature expansion.
 3. A temperature responsive warpage counteractingintegrated circuit assembly as claimed in claim 1 wherein said secondcoefficient of temperature expansion is greater than said firstcoefficient of temperature expansion.
 4. A temperature responsivewarpage counteracting integrated circuit assembly as claimed in claim 1wherein said first and second layers have aligned apertures therein. 5.A temperature responsive warpage counteracting integrated circuitassembly as claimed in claim 1 wherein said first layer has aplanar-convex cross section with the planar portion at said secondsurface.
 6. A temperature responsive warpage counteracting integratedcircuit assembly as claimed in claim 1 wherein said first layer has aplanar-concave cross section with the planar portion at said secondsurface.
 7. A temperature responsive warpage counteracting integratedcircuit assembly for use with an integrated circuit package having aconnection grid side and a top side, said integrated circuit assemblycomprising: a layer of a material having a coefficient of temperatureexpansion that varies from a first value at a first surface to a secondvalue at a second surface; said second surface of said layer of materialbonded to the top side of said integrated circuit package.
 8. Atemperature responsive warpage counteracting integrated circuit assemblyas claimed in claim 7 wherein said first value is greater than saidsecond value.
 9. A temperature responsive warpage counteractingintegrated circuit assembly as claimed in claim 7 wherein said secondvalue is greater than said first value.
 10. A temperature responsivewarpage counteracting integrated circuit assembly as claimed in claim 7wherein said layer has an aperture therein.
 11. A temperature responsivewarpage counteracting integrated circuit assembly as claimed in claim 7wherein said layer has planar-convex cross-section with the planarportion at said second surface.
 12. A temperature responsive warpagecounteracting integrated circuit assembly as claimed in claim 7 whereinsaid layer has planar-concave cross-section with the planar portion atsaid second surface.
 13. A method of manufacture of a temperatureresponsive warpage counteracting integrated circuit assembly for usewith an integrated circuit package having a connection grid side and atop side, said method comprising the steps of: providing a first layerof a first material having a first coefficient of temperature expansionand a first and second surface; providing a second layer of a secondmaterial having a second coefficient of temperature expansion differentfrom said first coefficient of temperature expansion and a first andsecond surface; bonding said first surface of said second layer to thesecond surface of said first layer; and bonding said second surface ofsecond layer to the top side of said integrated circuit package.
 14. Amethod of manufacture of a temperature responsive warpage counteractingintegrated circuit assembly as claimed in claim 13 comprising theadditional step of: providing that said first coefficient of temperatureexpansion is greater than said second coefficient of temperatureexpansion.
 15. A method of manufacture of a temperature responsivewarpage counteracting integrated circuit assembly as claimed in claim 13comprising the additional step of: providing that said secondcoefficient of temperature expansion is greater than said firstcoefficient of temperature expansion.
 16. A method of manufacture of atemperature responsive warpage counteracting integrated circuit assemblyas claimed in claim 13 comprising the additional step of: providing afirst aperture in said first layer; and providing a second aperture insaid second layer, wherein said second aperture is of generally the samesize as said first aperture, and aligned with said first aperture.
 17. Amethod of manufacture of a temperature responsive warpage counteractingintegrated circuit assembly for use with an integrated circuit packagehaving a connection grid side and a top side, said method comprising thesteps of: providing a layer of a material having a coefficient oftemperature expansion that varies from a first value at a first surfaceto a second value at a second surface; and bonding said second surfaceof said layer of material to the top side of said integrated circuitpackage.
 18. A method of manufacture of a temperature responsive warpagecounteracting integrated circuit assembly as claimed in claim 17comprising the additional step of: providing that said first value isgreater than said second value.
 19. A method of manufacture of atemperature responsive warpage counteracting integrated circuit assemblyas claimed in claim 17 comprising the additional step of: providing thatsaid second value is greater than said first value.
 20. A method ofmanufacture of a temperature responsive warpage counteracting integratedcircuit assembly as claimed in claim 17 comprising the additional stepof: providing an aperture in said layer.